Typically, in semiconductor chip applications, in a field effect transistor (FET), such as a junction gate field-effect transistor (JFET), there is a relationship between the pinchoff voltage Vp (the gate voltage at which the device will no longer conduct between the source and drain) and the on resistance Ron (the linear relationship between drain to source voltage and drain current for low drain to source voltage). Specifically, current methods of reducing Ron have the effect of increasing Vp. Therefore, it is difficult to fabricate a JFET device with a low Vp while maintaining a low Ron. In technologies with deep shallow trench isolations (STIs) and shallow diffusions, it is difficult to construct a standard JFET with a low Ron and low Vp. This is typically due to the fact that the JFET channel must extend underneath the STI and therefore the shallower gate junction provides less impact (or no contribution) to turning off the device (i.e., Vp).